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android
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drwxr-xr-x
2025-06-12 10:30
byteorder
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2025-06-12 10:30
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2025-06-12 10:30
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[ DIR ]
drwxr-xr-x
2025-06-12 10:30
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[ DIR ]
drwxr-xr-x
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[ DIR ]
drwxr-xr-x
2025-06-12 10:30
nfsd
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2025-06-12 10:30
raid
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drwxr-xr-x
2025-06-12 10:30
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drwxr-xr-x
2025-06-12 10:30
spi
[ DIR ]
drwxr-xr-x
2025-06-12 10:30
sunrpc
[ DIR ]
drwxr-xr-x
2025-06-12 10:30
tc_act
[ DIR ]
drwxr-xr-x
2025-06-12 10:30
tc_ematch
[ DIR ]
drwxr-xr-x
2025-06-12 10:30
usb
[ DIR ]
drwxr-xr-x
2025-06-12 10:30
wimax
[ DIR ]
drwxr-xr-x
2025-06-12 10:30
a.out.h
6.73
KB
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2025-05-21 15:48
acct.h
3.65
KB
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2025-05-21 15:48
adb.h
1.11
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2025-05-21 15:48
adfs_fs.h
936
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2025-05-21 15:48
affs_hardblocks.h
1.51
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2025-05-21 15:48
agpgart.h
3.85
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2025-05-21 15:48
aio_abi.h
3.34
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2025-05-21 15:48
am437x-vpfe.h
3.59
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2025-05-21 15:48
apm_bios.h
3.6
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arcfb.h
213
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arm_sdei.h
2.69
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2025-05-21 15:48
aspeed-lpc-ctrl.h
1.74
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atalk.h
1023
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atm.h
7.7
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atm_eni.h
648
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atm_he.h
406
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atm_idt77105.h
955
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atm_nicstar.h
1.25
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atm_tcp.h
1.58
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atm_zatm.h
1.5
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atmapi.h
952
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atmarp.h
1.27
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atmbr2684.h
3.19
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atmclip.h
576
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atmdev.h
7.5
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atmioc.h
1.61
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atmlec.h
2.33
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atmmpc.h
4.13
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atmppp.h
639
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atmsap.h
4.85
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atmsvc.h
1.81
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audit.h
19.92
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auto_dev-ioctl.h
4.87
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auto_fs.h
6.28
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auto_fs4.h
451
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auxvec.h
1.56
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ax25.h
2.76
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b1lli.h
1.68
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batadv_packet.h
20.01
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batman_adv.h
11.7
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baycom.h
883
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bcache.h
8.17
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bcm933xx_hcs.h
419
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bfs_fs.h
1.85
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binfmts.h
628
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blkpg.h
904
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blktrace_api.h
4.59
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blkzoned.h
6.45
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bpf.h
223.3
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bpf_common.h
1.33
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bpf_perf_event.h
529
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bpfilter.h
465
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bpqether.h
981
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bsg.h
2.44
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bt-bmc.h
572
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btf.h
4.68
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btrfs.h
28.24
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2025-05-21 15:48
btrfs_tree.h
24.69
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can.h
7.7
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2025-05-21 15:48
capability.h
13.2
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2025-05-21 15:48
capi.h
3.05
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cciss_defs.h
3.2
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cciss_ioctl.h
2.7
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cdrom.h
28.18
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cec-funcs.h
52.64
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cec.h
36.81
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cfm_bridge.h
1.42
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2025-05-21 15:48
cgroupstats.h
2.17
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2025-05-21 15:48
chio.h
5.22
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2025-05-21 15:48
close_range.h
377
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cm4000_cs.h
1.76
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cn_proc.h
3.38
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2025-05-21 15:48
coda.h
17.09
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2025-05-21 15:48
coda_psdev.h
783
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2025-05-21 15:48
coff.h
12.18
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2025-05-21 15:48
connector.h
2.2
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const.h
788
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coresight-stm.h
674
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cramfs_fs.h
3.47
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2025-05-21 15:48
cryptouser.h
3.31
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2025-05-21 15:48
cuda.h
905
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cyclades.h
16.71
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cycx_cfm.h
2.92
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dcbnl.h
24.65
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dccp.h
6.29
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devlink.h
21.05
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dlm.h
2.49
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dlm_device.h
2.48
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dlm_netlink.h
1.13
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dlm_plock.h
894
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dlmconstants.h
4.96
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dm-ioctl.h
11.13
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dm-log-userspace.h
14.83
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dma-buf.h
5.12
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dn.h
4.53
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dqblk_xfs.h
9.03
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edd.h
5.47
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efs_fs_sb.h
2.17
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elf-em.h
2.14
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elf-fdpic.h
1.1
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elf.h
13.16
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elfcore.h
2.92
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errno.h
23
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errqueue.h
1.44
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erspan.h
1.03
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ethtool.h
81.89
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ethtool_netlink.h
22.29
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eventpoll.h
2.67
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fadvise.h
842
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falloc.h
3.5
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fanotify.h
5.22
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fb.h
16.09
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fcntl.h
4.08
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fd.h
11.4
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fdreg.h
5.29
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fib_rules.h
1.99
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fiemap.h
2.71
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filter.h
2.16
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firewire-cdev.h
42.86
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firewire-constants.h
3.16
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flat.h
2.1
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fou.h
694
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fpga-dfl.h
8.52
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fs.h
13.11
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fsl_hypervisor.h
7.13
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2025-05-21 15:48
fsmap.h
4.29
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fuse.h
22.92
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futex.h
4.88
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gameport.h
897
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gen_stats.h
1.49
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genetlink.h
2.12
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gfs2_ondisk.h
14.4
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gigaset_dev.h
1.41
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2025-05-21 15:48
gpio.h
6.59
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2025-05-21 15:48
gsmmux.h
1.02
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gtp.h
681
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hash_info.h
921
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hdlc.h
637
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hdlcdrv.h
2.84
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hdreg.h
22.17
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hid.h
1.86
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hiddev.h
6.2
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hidraw.h
1.95
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hpet.h
743
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2025-05-21 15:48
hsr_netlink.h
1.06
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hw_breakpoint.h
742
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hyperv.h
10.89
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2025-05-21 15:48
hysdn_if.h
1.35
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i2c-dev.h
2.55
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2025-05-21 15:48
i2c.h
6.96
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2025-05-21 15:48
i2o-dev.h
11.28
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2025-05-21 15:48
i8k.h
1.49
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icmp.h
2.91
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2025-05-21 15:48
icmpv6.h
3.94
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2025-05-21 15:48
idxd.h
8.22
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2025-05-21 15:48
if.h
10.65
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if_addr.h
1.84
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if_addrlabel.h
721
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if_alg.h
946
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if_arcnet.h
3.63
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if_arp.h
6.42
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if_bonding.h
5.17
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if_bridge.h
19.06
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if_cablemodem.h
986
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if_eql.h
1.32
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if_ether.h
8.05
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if_fc.h
1.7
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if_fddi.h
3.66
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if_frad.h
2.95
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if_hippi.h
4.14
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if_infiniband.h
1.22
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if_link.h
30.28
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if_ltalk.h
210
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if_macsec.h
5.7
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if_packet.h
7.73
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if_phonet.h
424
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if_plip.h
660
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if_ppp.h
29
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if_pppol2tp.h
3.21
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if_pppox.h
4.76
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if_slip.h
872
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if_team.h
2.54
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if_tun.h
4
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if_tunnel.h
4.41
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if_vlan.h
1.79
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if_x25.h
881
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if_xdp.h
2.94
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ife.h
351
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igmp.h
2.99
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ila.h
1.22
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in.h
9.78
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in6.h
7.26
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in_route.h
936
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inet_diag.h
4.56
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inotify.h
3.21
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2025-05-21 15:48
input-event-codes.h
27.94
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2025-05-21 15:48
input.h
15.61
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2025-05-21 15:48
io_uring.h
6.06
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ioctl.h
163
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iommu.h
4.79
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2025-05-21 15:48
ip.h
4.62
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2025-05-21 15:48
ip6_tunnel.h
1.91
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2025-05-21 15:48
ip_vs.h
13.31
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2025-05-21 15:48
ipc.h
2.05
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2025-05-21 15:48
ipmi.h
15.08
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ipmi_bmc.h
464
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msg.h
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netdevice.h
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netfilter_arp.h
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netfilter_decnet.h
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netlink_diag.h
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netrom.h
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nexthop.h
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nfc.h
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nfs.h
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nfsacl.h
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nl80211.h
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nsfs.h
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nvme_ioctl.h
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nvram.h
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openat2.h
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openvswitch.h
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packet_diag.h
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param.h
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parport.h
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patchkey.h
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pci.h
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pci_regs.h
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pcitest.h
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perf_event.h
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personality.h
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pfkeyv2.h
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pfrut.h
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pg.h
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phantom.h
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phonet.h
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pkt_cls.h
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pkt_sched.h
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pktcdvd.h
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pmu.h
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poll.h
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posix_types.h
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ppdev.h
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ppp-comp.h
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ppp-ioctl.h
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ppp_defs.h
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pps.h
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pr.h
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prctl.h
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psample.h
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psci.h
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psp-sev.h
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ptp_clock.h
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ptrace.h
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qemu_fw_cfg.h
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qnx4_fs.h
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qnxtypes.h
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qrtr.h
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quota.h
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radeonfb.h
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random.h
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raw.h
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rds.h
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reboot.h
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reiserfs_fs.h
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reiserfs_xattr.h
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resource.h
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rfkill.h
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rio_cm_cdev.h
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rio_mport_cdev.h
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romfs_fs.h
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rose.h
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route.h
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rpmsg.h
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rseq.h
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rtc.h
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rtnetlink.h
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rxrpc.h
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scc.h
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sched.h
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scif_ioctl.h
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screen_info.h
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sctp.h
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sdla.h
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seccomp.h
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securebits.h
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sed-opal.h
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seg6.h
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seg6_genl.h
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seg6_hmac.h
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seg6_iptunnel.h
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seg6_local.h
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selinux_netlink.h
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sem.h
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serial.h
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serial_core.h
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serial_reg.h
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serio.h
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sev-guest.h
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shm.h
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signal.h
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signalfd.h
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smc.h
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smc_diag.h
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smiapp.h
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snmp.h
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sock_diag.h
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socket.h
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sockios.h
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sonet.h
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sonypi.h
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sound.h
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soundcard.h
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stat.h
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stddef.h
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stm.h
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string.h
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suspend_ioctls.h
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swab.h
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switchtec_ioctl.h
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sync_file.h
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synclink.h
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sysctl.h
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sysinfo.h
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target_core_user.h
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taskstats.h
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tcp.h
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tcp_metrics.h
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tdx-guest.h
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tee.h
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termios.h
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thermal.h
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time.h
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time_types.h
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timerfd.h
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times.h
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timex.h
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tiocl.h
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tipc.h
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tipc_config.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $ * linux/include/linux/cyclades.h * * This file was initially written by * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by * Ivan Passos <ivan@cyclades.com>. * * This file contains the general definitions for the cyclades.c driver *$Log: cyclades.h,v $ *Revision 3.1 2002/01/29 11:36:16 henrique *added throttle field on struct cyclades_port to indicate whether the *port is throttled or not * *Revision 3.1 2000/04/19 18:52:52 ivan *converted address fields to unsigned long and added fields for physical *addresses on cyclades_card structure; * *Revision 3.0 1998/11/02 14:20:59 ivan *added nports field on cyclades_card structure; * *Revision 2.5 1998/08/03 16:57:01 ivan *added cyclades_idle_stats structure; * *Revision 2.4 1998/06/01 12:09:53 ivan *removed closing_wait2 from cyclades_port structure; * *Revision 2.3 1998/03/16 18:01:12 ivan *changes in the cyclades_port structure to get it closer to the *standard serial port structure; *added constants for new ioctls; * *Revision 2.2 1998/02/17 16:50:00 ivan *changes in the cyclades_port structure (addition of shutdown_wait and *chip_rev variables); *added constants for new ioctls and for CD1400 rev. numbers. * *Revision 2.1 1997/10/24 16:03:00 ivan *added rflow (which allows enabling the CD1400 special flow control *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to *cyclades_port structure; *added Alpha support * *Revision 2.0 1997/06/30 10:30:00 ivan *added some new doorbell command constants related to IOCTLW and *UART error signaling * *Revision 1.8 1997/06/03 15:30:00 ivan *added constant ZFIRM_HLT *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin) * *Revision 1.7 1997/03/26 10:30:00 daniel *new entries at the end of cyclades_port struct to reallocate *variables illegally allocated within card memory. * *Revision 1.6 1996/09/09 18:35:30 bentson *fold in changes for Cyclom-Z -- including structures for *communicating with board as well modest changes to original *structures to support new features. * *Revision 1.5 1995/11/13 21:13:31 bentson *changes suggested by Michael Chastain <mec@duracef.shout.net> *to support use of this file in non-kernel applications * * */ #ifndef _LINUX_CYCLADES_H #define _LINUX_CYCLADES_H #include <linux/types.h> struct cyclades_monitor { unsigned long int_count; unsigned long char_count; unsigned long char_max; unsigned long char_last; }; /* * These stats all reflect activity since the device was last initialized. * (i.e., since the port was opened with no other processes already having it * open) */ struct cyclades_idle_stats { __kernel_time_t in_use; /* Time device has been in use (secs) */ __kernel_time_t recv_idle; /* Time since last char received (secs) */ __kernel_time_t xmit_idle; /* Time since last char transmitted (secs) */ unsigned long recv_bytes; /* Bytes received */ unsigned long xmit_bytes; /* Bytes transmitted */ unsigned long overruns; /* Input overruns */ unsigned long frame_errs; /* Input framing errors */ unsigned long parity_errs; /* Input parity errors */ }; #define CYCLADES_MAGIC 0x4359 #define CYGETMON 0x435901 #define CYGETTHRESH 0x435902 #define CYSETTHRESH 0x435903 #define CYGETDEFTHRESH 0x435904 #define CYSETDEFTHRESH 0x435905 #define CYGETTIMEOUT 0x435906 #define CYSETTIMEOUT 0x435907 #define CYGETDEFTIMEOUT 0x435908 #define CYSETDEFTIMEOUT 0x435909 #define CYSETRFLOW 0x43590a #define CYGETRFLOW 0x43590b #define CYSETRTSDTR_INV 0x43590c #define CYGETRTSDTR_INV 0x43590d #define CYZSETPOLLCYCLE 0x43590e #define CYZGETPOLLCYCLE 0x43590f #define CYGETCD1400VER 0x435910 #define CYSETWAIT 0x435912 #define CYGETWAIT 0x435913 /*************** CYCLOM-Z ADDITIONS ***************/ #define CZIOC ('M' << 8) #define CZ_NBOARDS (CZIOC|0xfa) #define CZ_BOOT_START (CZIOC|0xfb) #define CZ_BOOT_DATA (CZIOC|0xfc) #define CZ_BOOT_END (CZIOC|0xfd) #define CZ_TEST (CZIOC|0xfe) #define CZ_DEF_POLL (HZ/25) #define MAX_BOARD 4 /* Max number of boards */ #define MAX_DEV 256 /* Max number of ports total */ #define CYZ_MAX_SPEED 921600 #define CYZ_FIFO_SIZE 16 #define CYZ_BOOT_NWORDS 0x100 struct CYZ_BOOT_CTRL { unsigned short nboard; int status[MAX_BOARD]; int nchannel[MAX_BOARD]; int fw_rev[MAX_BOARD]; unsigned long offset; unsigned long data[CYZ_BOOT_NWORDS]; }; #ifndef DP_WINDOW_SIZE /* * Memory Window Sizes */ #define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */ #define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and 8Zo V.2 */ #define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */ /* * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver * normally will access only interested on the fpga_id, fpga_version, * start_cpu and stop_cpu. */ struct CUSTOM_REG { __u32 fpga_id; /* FPGA Identification Register */ __u32 fpga_version; /* FPGA Version Number Register */ __u32 cpu_start; /* CPU start Register (write) */ __u32 cpu_stop; /* CPU stop Register (write) */ __u32 misc_reg; /* Miscellaneous Register */ __u32 idt_mode; /* IDT mode Register */ __u32 uart_irq_status; /* UART IRQ status Register */ __u32 clear_timer0_irq; /* Clear timer interrupt Register */ __u32 clear_timer1_irq; /* Clear timer interrupt Register */ __u32 clear_timer2_irq; /* Clear timer interrupt Register */ __u32 test_register; /* Test Register */ __u32 test_count; /* Test Count Register */ __u32 timer_select; /* Timer select register */ __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ __u32 ram_wait_state; /* RAM wait-state Register */ __u32 uart_wait_state; /* UART wait-state Register */ __u32 timer_wait_state; /* timer wait-state Register */ __u32 ack_wait_state; /* ACK wait State Register */ }; /* * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime * registers. This structure can be used to access the 9060 registers * (memory mapped). */ struct RUNTIME_9060 { __u32 loc_addr_range; /* 00h - Local Address Range */ __u32 loc_addr_base; /* 04h - Local Address Base */ __u32 loc_arbitr; /* 08h - Local Arbitration */ __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */ __u32 loc_rom_range; /* 10h - Local ROM Range */ __u32 loc_rom_base; /* 14h - Local ROM Base */ __u32 loc_bus_descr; /* 18h - Local Bus descriptor */ __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */ __u32 loc_base_mst; /* 20h - Local Base for Master PCI */ __u32 loc_range_io; /* 24h - Local Range for Master IO */ __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */ __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */ __u32 filler1; /* 30h */ __u32 filler2; /* 34h */ __u32 filler3; /* 38h */ __u32 filler4; /* 3Ch */ __u32 mail_box_0; /* 40h - Mail Box 0 */ __u32 mail_box_1; /* 44h - Mail Box 1 */ __u32 mail_box_2; /* 48h - Mail Box 2 */ __u32 mail_box_3; /* 4Ch - Mail Box 3 */ __u32 filler5; /* 50h */ __u32 filler6; /* 54h */ __u32 filler7; /* 58h */ __u32 filler8; /* 5Ch */ __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */ __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */ __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */ __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */ }; /* Values for the Local Base Address re-map register */ #define WIN_RAM 0x00000001L /* set the sliding window to RAM */ #define WIN_CREG 0x14000001L /* set the window to custom Registers */ /* Values timer select registers */ #define TIMER_BY_1M 0x00 /* clock divided by 1M */ #define TIMER_BY_256K 0x01 /* clock divided by 256k */ #define TIMER_BY_128K 0x02 /* clock divided by 128k */ #define TIMER_BY_32K 0x03 /* clock divided by 32k */ /****************** ****************** *******************/ #endif #ifndef ZFIRM_ID /* #include "zfwint.h" */ /****************** ****************** *******************/ /* * This file contains the definitions for interfacing with the * Cyclom-Z ZFIRM Firmware. */ /* General Constant definitions */ #define MAX_CHAN 64 /* max number of channels per board */ /* firmware id structure (set after boot) */ #define ID_ADDRESS 0x00000180L /* signature/pointer address */ #define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */ #define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */ #define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */ #define ZF_TINACT_DEF 1000 /* default inactivity timeout (1000 ms) */ #define ZF_TINACT ZF_TINACT_DEF struct FIRM_ID { __u32 signature; /* ZFIRM/U signature */ __u32 zfwctrl_addr; /* pointer to ZFW_CTRL structure */ }; /* Op. System id */ #define C_OS_LINUX 0x00000030 /* generic Linux system */ /* channel op_mode */ #define C_CH_DISABLE 0x00000000 /* channel is disabled */ #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */ #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */ #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */ #define C_CH_LOOPBACK 0x00000004 /* Loopback mode */ /* comm_parity - parity */ #define C_PR_NONE 0x00000000 /* None */ #define C_PR_ODD 0x00000001 /* Odd */ #define C_PR_EVEN 0x00000002 /* Even */ #define C_PR_MARK 0x00000004 /* Mark */ #define C_PR_SPACE 0x00000008 /* Space */ #define C_PR_PARITY 0x000000ff #define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */ #define C_PR_IGNORE 0x00000200 /* ignore frame/par error */ /* comm_data_l - data length and stop bits */ #define C_DL_CS5 0x00000001 #define C_DL_CS6 0x00000002 #define C_DL_CS7 0x00000004 #define C_DL_CS8 0x00000008 #define C_DL_CS 0x0000000f #define C_DL_1STOP 0x00000010 #define C_DL_15STOP 0x00000020 #define C_DL_2STOP 0x00000040 #define C_DL_STOP 0x000000f0 /* interrupt enabling/status */ #define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */ #define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */ #define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */ #define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */ #define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */ #define C_IN_MDCD 0x00000100 /* modem DCD change */ #define C_IN_MDSR 0x00000200 /* modem DSR change */ #define C_IN_MRI 0x00000400 /* modem RI change */ #define C_IN_MCTS 0x00000800 /* modem CTS change */ #define C_IN_RXBRK 0x00001000 /* Break received */ #define C_IN_PR_ERROR 0x00002000 /* parity error */ #define C_IN_FR_ERROR 0x00004000 /* frame error */ #define C_IN_OVR_ERROR 0x00008000 /* overrun error */ #define C_IN_RXOFL 0x00010000 /* RX buffer overflow */ #define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */ #define C_IN_MRTS 0x00040000 /* modem RTS drop */ #define C_IN_ICHAR 0x00080000 /* flow control */ #define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */ #define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */ #define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */ #define C_FL_SWFLOW 0x0000000f /* flow status */ #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ #define C_FS_SENDING 0x00000001 /* UART is sending data */ #define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */ /* rs_control/rs_status RS-232 signals */ #define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in IOCTLM command */ #define C_RS_RTS 0x00000001 /* RTS */ #define C_RS_DTR 0x00000004 /* DTR */ #define C_RS_DCD 0x00000100 /* CD */ #define C_RS_DSR 0x00000200 /* DSR */ #define C_RS_RI 0x00000400 /* RI */ #define C_RS_CTS 0x00000800 /* CTS */ /* commands Host <-> Board */ #define C_CM_RESET 0x01 /* reset/flush buffers */ #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */ #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */ #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */ #define C_CM_SENDXOFF 0x10 /* send Xoff */ #define C_CM_SENDXON 0x11 /* send Xon */ #define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */ #define C_CM_SENDBRK 0x41 /* send break */ #define C_CM_INTBACK 0x42 /* Interrupt back */ #define C_CM_SET_BREAK 0x43 /* Tx break on */ #define C_CM_CLR_BREAK 0x44 /* Tx break off */ #define C_CM_CMD_DONE 0x45 /* Previous command done */ #define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */ #define C_CM_TINACT 0x51 /* set inactivity detection */ #define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */ #define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */ #define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */ #define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */ #define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */ #define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */ #define C_CM_Q_ENABLE 0x58 /* enables queue access from the driver */ #define C_CM_Q_DISABLE 0x59 /* disables queue access from the driver */ #define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */ #define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */ #define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */ #define C_CM_RXNNDT 0x63 /* rx no new data timeout */ #define C_CM_TXFEMPTY 0x64 #define C_CM_ICHAR 0x65 #define C_CM_MDCD 0x70 /* modem DCD change */ #define C_CM_MDSR 0x71 /* modem DSR change */ #define C_CM_MRI 0x72 /* modem RI change */ #define C_CM_MCTS 0x73 /* modem CTS change */ #define C_CM_MRTS 0x74 /* modem RTS drop */ #define C_CM_RXBRK 0x84 /* Break received */ #define C_CM_PR_ERROR 0x85 /* Parity error */ #define C_CM_FR_ERROR 0x86 /* Frame error */ #define C_CM_OVR_ERROR 0x87 /* Overrun error */ #define C_CM_RXOFL 0x88 /* RX buffer overflow */ #define C_CM_CMDERROR 0x90 /* command error */ #define C_CM_FATAL 0x91 /* fatal error */ #define C_CM_HW_RESET 0x92 /* reset board */ /* * CH_CTRL - This per port structure contains all parameters * that control an specific port. It can be seen as the * configuration registers of a "super-serial-controller". */ struct CH_CTRL { __u32 op_mode; /* operation mode */ __u32 intr_enable; /* interrupt masking */ __u32 sw_flow; /* SW flow control */ __u32 flow_status; /* output flow status */ __u32 comm_baud; /* baud rate - numerically specified */ __u32 comm_parity; /* parity */ __u32 comm_data_l; /* data length/stop */ __u32 comm_flags; /* other flags */ __u32 hw_flow; /* HW flow control */ __u32 rs_control; /* RS-232 outputs */ __u32 rs_status; /* RS-232 inputs */ __u32 flow_xon; /* xon char */ __u32 flow_xoff; /* xoff char */ __u32 hw_overflow; /* hw overflow counter */ __u32 sw_overflow; /* sw overflow counter */ __u32 comm_error; /* frame/parity error counter */ __u32 ichar; __u32 filler[7]; }; /* * BUF_CTRL - This per channel structure contains * all Tx and Rx buffer control for a given channel. */ struct BUF_CTRL { __u32 flag_dma; /* buffers are in Host memory */ __u32 tx_bufaddr; /* address of the tx buffer */ __u32 tx_bufsize; /* tx buffer size */ __u32 tx_threshold; /* tx low water mark */ __u32 tx_get; /* tail index tx buf */ __u32 tx_put; /* head index tx buf */ __u32 rx_bufaddr; /* address of the rx buffer */ __u32 rx_bufsize; /* rx buffer size */ __u32 rx_threshold; /* rx high water mark */ __u32 rx_get; /* tail index rx buf */ __u32 rx_put; /* head index rx buf */ __u32 filler[5]; /* filler to align structures */ }; /* * BOARD_CTRL - This per board structure contains all global * control fields related to the board. */ struct BOARD_CTRL { /* static info provided by the on-board CPU */ __u32 n_channel; /* number of channels */ __u32 fw_version; /* firmware version */ /* static info provided by the driver */ __u32 op_system; /* op_system id */ __u32 dr_version; /* driver version */ /* board control area */ __u32 inactivity; /* inactivity control */ /* host to FW commands */ __u32 hcmd_channel; /* channel number */ __u32 hcmd_param; /* pointer to parameters */ /* FW to Host commands */ __u32 fwcmd_channel; /* channel number */ __u32 fwcmd_param; /* pointer to parameters */ __u32 zf_int_queue_addr; /* offset for INT_QUEUE structure */ /* filler so the structures are aligned */ __u32 filler[6]; }; /* Host Interrupt Queue */ #define QUEUE_SIZE (10*MAX_CHAN) struct INT_QUEUE { unsigned char intr_code[QUEUE_SIZE]; unsigned long channel[QUEUE_SIZE]; unsigned long param[QUEUE_SIZE]; unsigned long put; unsigned long get; }; /* * ZFW_CTRL - This is the data structure that includes all other * data structures used by the Firmware. */ struct ZFW_CTRL { struct BOARD_CTRL board_ctrl; struct CH_CTRL ch_ctrl[MAX_CHAN]; struct BUF_CTRL buf_ctrl[MAX_CHAN]; }; /****************** ****************** *******************/ #endif #endif /* _LINUX_CYCLADES_H */